1. Field of the Invention
The present invention relates to frequency division of an input clock signal. In particular, the present invention relates to circuitry for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer.
2. Discussion of the Related Art
Digital frequency synthesizer circuits, such as phase locked loop (PLL) digital frequency synthesizer circuits, are operable at high speeds and are typically used in digital mobile communication devices. A conventional PLL frequency synthesizer circuit includes a frequency divider which has a prescaler, such as a dual modulus prescaler. A prescaler is used to generate narrowly-spaced frequencies at frequencies which are too high to be reliably passed through a feedback system of a device. A dual modulus prescaler selectively frequency divides a frequency signal (e.g. an input clock signal from a voltage controlled oscillator (VCO)) by either a frequency dividing ratio k or a frequency-dividing ratio (k+x) to supply a frequency-divided signal. The modulus of a prescaler is its division ratio. A dual modulus prescaler can divide by two different factors, such as k and k+x. x may be positive or negative, and may for example be 1. A control input can be used to switch the factor used by the prescaler between k and k+x.
One example of a dual modulus prescaler which is based on a shift register ring is shown in FIG. 1a. The flip flops (102, 104, 106, 112 and 116) FIG. 1a are initialized to output high signals. FIG. 1b shows a timing diagram of signals output from the flip flops 102, 104, 106 and 116 in the dual-modulus prescaler of FIG. 1a when M is set to 0. It can be seen that when M is set to 0 the output signal has a frequency which is eight times less than the frequency of the input clock signal. FIG. 1c shows a timing diagram of signals output from the flip flops 102, 104, 106, 112 and 116 in the dual-modulus prescaler of FIG. 1a when M is set to 1. It can be seen that when M is set to 1 the output signal has a frequency which is nine times less than the frequency of the input clock signal.
Another example of a dual modulus prescaler is shown in FIG. 2a which uses cascaded divide-by-two stages (202, 204 and 206), as described in “High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler” by Patrik Larsson, IEEE Journal on Solid-State Circuits, VOL. 31, No. 5, May 1996. The one detector 208 gives a low output pulse when the M signal and the outputs of all divide-buy-two stages (202, 204 and 206) are high. This pulse is delayed one clock cycle and synchronized with the inverted input clock signal in the D flip-flop 212. The input clock signal may, for example, be received from a voltage controlled oscillator (VCO). A low output from the D flip flop 212 will prohibit one negative pulse of the Clk signal from reaching the first divide-by-two stage 202. After cancelling one clock pulse, it will take eight clock pulses before the one detector 208 output goes low, giving a division ratio of nine. By setting M low, the detector output is always high and the prescaler divides by eight. Therefore the circuit operates as an 8/9 prescaler, using M as the control signal, but can be easily modified to a 2b/2b+1 prescaler by adding or removing divide-by-two stages thereby extending or shortening the detector. FIG. 2b shows a timing diagram of signals output from the divide-by-two stages 202, 204 and 206 and from the D flip flop 212 in the dual-modulus prescaler of FIG. 2a when M is set to 0. It can be seen that when M is set to 0 the output signal has a frequency which is eight times less than the frequency of the input clock signal. FIG. 1c shows a timing diagram of signals output from the divide-by-two stages 202, 204 and 206 and from the D flip flop 212 in the dual-modulus prescaler of FIG. 1a when M is set to 1. It can be seen that when M is set to 1 the output signal has a frequency which is nine times less than the frequency of the input clock signal.